Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Join a team of design and verification engineers, collaboratively working with others to comprehend and validate the functionality of a given design element within the context of the block, chip and overall system.
Ensure that the test plan, containing directed and constrained-random tests, is meticulously documented and executed during simulation.
Evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure.
Proven experience of over 10 years in verification for large ASIC projects, or software/firmware development in a hardware setting.
A robust skill set in C/C++ development within a Linux environment.
Over ten years’ experience in UVM, Verilog, and C++
