Description
<p><b>ASIC DV Engineer </b></p><p>Location: Remote- Canada </p><p> </p><p>• The candidate would work closely with a team of designers, architects, and verification engineers to design and implement various display technologies.</p><p> </p><p>KEY RESPONSIBILITIES:</p><p>• Develop well designed and qualified display features</p><p>• Lead micro-architecture and design efforts based on high level architectural requirements</p><p>• Able to build complex systems to meet various design requirements including (but not limited to) functionality, performance, power, area, scalability and testability.</p><p>• Timely develop functional and implementation specifications, as well as test plans</p><p>• Develop and execute implementation and validation plans of the feature. Proactively driving and resolving any issues that may arise during the development stage</p><p>• Resolve pre-layout and post-layout timing and functional eco issues</p><p>• Mentor junior engineers to complete their tasks.</p><p> </p><p>PREFERRED EXPERIENCE:</p><p>• Minimum 7 years of ASIC design work experience</p><p>• Have in depth knowledge of entire design process from design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, timing and formal verification</p><p>• Proficiency of Verilog or SystemVerilog</p><p>• Experience with multi-clock domain designs</p><p>• Experience in IP development</p><p>• Knowledge in video/display standards a plus.</p><p>• Strong in both written and verbal communication</p><p>• Strong analytical thinking and problem-solving skills</p><p>• Good teamwork and interpersonal skills </p><p><b>ARM GLS Skill set.</b></p><ul><li>Good DV Skill with major GLS work experience. </li><li>Expertise in testbench updates for GLS </li><li>Expertise in Scripting languages perl or python</li><li>Experience with Make, Yaml & Json file systems.</li><li>Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis).</li><li>Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows.</li><li>Experience with flow optimizations such as Grey/Black-boxing techniques</li><li>Good at communicating requirements/issues with Implementation, PnR and Design teams.</li><li>Working knowledge of Confluence documentation , version system GIT and Project execution with JIRA.</li></ul><p> </p><p><br></p><p><b>Thanks & Regards</b></p><p><b>Sameer Ahmad </b></p><p>Raas Infotek Corporation. </p><p>262 Chapman Road, Suite 105A, </p><p>Newark, DE -19702 </p><p>Phone: (302) 565-0068 Ext: 143 </p><p>E-Mail: sameer.ahmad@raasinfotek.com|Website: www.raasinfotek.com </p><p>Linkedin: linkedin.com/in/sameer-ahmad-031a0b185</p><p></p>
