Description

Job Title

Debug Sub-System & Design-for-Test (DFT) Engineer

Summary

We are seeking a Debug Sub-System / DFT Engineer to architect, implement, and validate the on-chip debug and test infrastructure for complex SoC and ASIC designs. This role spans the full lifecycle — from specification and RTL design of debug/DFT features through pre-silicon verification, ATPG pattern generation, and post-silicon validation. The ideal candidate combines deep DFT methodology expertise with knowledge of silicon debug subsystems, enabling efficient manufacturing test, in-field diagnostics, and post-silicon debug.

Key Responsibilities

Debug Sub-System Design & Integration

  • Understanding of on-chip debug infrastructure including:
  • JTAG TAP controllers (IEEE 1149.1/1149.6) and daisy-chain/star topologies
  • CoreSight / ARM Debug Architecture (DAP, SWD, ETM, CTI, cross-trigger matrices)
  • Trace infrastructure (ETB, ETR, TPIU, trace funnels, timestamps)
  • Embedded Logic Analyzers (ELA) / on-chip signal monitors
  • Debug authentication and security (secure debug, debug access levels, lock/unlock)
  • Design and integrate DFx (Design for Debug/Diagnostics) features:
  • Performance counters and event monitors
  • Error logging and first-error capture registers
  • Signal observation via debug muxes and pad multiplexing
  • Register access over debug ports (JTAG-to-APB/AHB/AXI bridges)
  • Debug subsystem interconnect (debug bus, cross-trigger fabric, power-domain-aware debug access)
  • Collaborate with architecture teams on debug use cases: boot debug, crash analysis, performance profiling, in-field diagnostics

Design-for-Test (DFT)

  • Understand DFT architecture for complex SoC designs, including:
  • Scan insertion: full scan, compressed scan (Tessent, Modus, DFT Compiler)
  • Memory BIST (MBIST): controller design, repair logic, redundancy allocation
  • Logic BIST (LBIST): self-test controllers, PRPG, MISR, fault coverage analysis
  • Boundary Scan (JTAG): BSR chain design, IEEE 1149.1 compliance
  • At-speed testing: launch-on-shift, launch-on-capture, multi-clock domain handling
  • Drive ATPG pattern generation and achieve target fault coverage (stuck-at, transition, path delay, bridging)
  • Implement test compression (DFTMAX, Tessent TestKompress, EDT) to reduce test data volume and ATE test time
  • Design DFT for low-power: isolation, retention scan, UPF-aware DFT insertion
  • Handle analog/mixed-signal test interfaces (ADC/DAC BIST, PLL test modes, SerDes loopback)
  • Define and implement test access mechanisms (TAM): wrapper chains, hierarchical test, IEEE 1500 wrappers for IP cores

Verification & Validation (Most Important)

  • Verify DFT/debug RTL through simulation and formal methods:
  • JTAG TAP compliance tests
  • Scan chain integrity checks
  • MBIST/LBIST functional verification
  • Debug authentication sequence validation
  • Run DRC (Design Rule Checks) for DFT: scan rule violations, clock gating, X-sources, hold-time fixes
  • Perform ATPG dry runs and iterate on coverage closure with design teams
  • Support post-silicon DFT validation: scan pattern bring-up, MBIST execution, yield debug
  • Debug test escapes and drive corrective actions (pattern update, DFT ECO, coverage gap closure)

Manufacturing Test & Yield

  • Collaborate with test engineering and ATE teams on test program development
  • Optimize test cost: pattern count, test time, multi-site efficiency, compression ratio
  • Support yield analysis and diagnosis: failing pattern debug, defect localization, systematic vs. random fail classification
  • Develop and maintain DFT documentation: test architecture specs, coverage reports, test insertion guidelines

Required Qualifications

  • Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field
  • Experience: 4–10+ years in DFT, debug subsystem design, or silicon test engineering
  • Strong expertise in one or both domains:
  • Proficiency in RTL design using Verilog/SystemVerilog
  • Experience with industry DFT tools:
  • Knowledge of JTAG/IEEE 1149.1 standard and TAP controller state machine
  • Experience with ATPG pattern generation, fault models (SA0/SA1, transition, IDDQ), and coverage analysis
  • Familiarity with memory test (March algorithms, repair, redundancy, fuse programming)
  • Strong scripting skills: Tcl, Python, Perl for tool automation and flow development
  • Understanding of SoC integration and multi-IP DFT challenges